1. Field of the Invention
The present invention relates to a semiconductor device, and especially to a high voltage IC (hereinafter referred to as an xe2x80x9cHVICxe2x80x9d) comprising a bootstrap diode.
2. Description of the Background Art
FIG. 29 is a circuit diagram of a conventional HVIC 110 and its peripheral circuits. As shown in FIG. 29, the conventional HVIC 110 comprises a bootstrap diode 102 and a logic circuit 103 formed in a high-potential island region 101. In the periphery of the HVIC 110, a bootstrap capacitance 200 is located in parallel with the logic circuit 103. A cathode of the bootstrap diode 102 is connected to one end of the logic circuit 103. A voltage source 150L is connected to an anode of the bootstrap diode 102.
Now, operations in the circuit diagram of FIG. 29 will be set forth. When a voltage at the voltage source 150L is higher than that at a virtual voltage source 150H which is a virtual variable voltage source for determining a potential at the other end of the logic circuit 103, the bootstrap diode 102 is forward biased and the voltage is supplied from the voltage source 150L to the logic circuit 103. At this time, an electric charge is applied to the bootstrap capacitance 200 and a potential at the cathode of the bootstrap diode 102 rises to (V1xe2x88x92Vrec), where Vrec is the forward voltage of the bootstrap diode 102 and V1 is the voltage at the voltage source 150L.
When, with the bootstrap capacitance 200 charged, the voltage at the virtual voltage source 150H increases by xcex94V ( greater than Vrec), the potential at the cathode of the bootstrap diode 102 becomes V1xe2x88x92Vrec+xcex94V ( greater than V1). The bootstrap diode 102 is thus reverse biased and the current supply from the voltage source 150L to the logic circuit 103 comes to a stop. At this time, the electric charge on the bootstrap capacitance 200 is supplied to the logic circuit 103.
FIG. 30 is a schematic plan view of a configuration of the conventional HVIC 110, and FIG. 31 is a cross-sectional view taken along the line Fxe2x80x94F indicated by the arrows. To avoid the complexity of the drawing, an insulating film 8 of FIG. 31 is not shown in FIG. 30, which shows only a cathode and an anode electrodes 15, 16 of the bootstrap diode 102 and a metal electrode 14, out of the electrodes formed on an insulating film 18. The conventional HVIC 110 utilizes a RESURF (reduced surface field) effect to provide isolation between the logic circuit 103 and the bootstrap diode 102.
In the conventional HVIC 110, as shown in FIGS. 30 and 31, an nxe2x88x92 semiconductor layer 3 is formed on a pxe2x88x92 semiconductor substrate 1. An n+ buried impurity region 2 is selectively formed at the interface between the pxe2x88x92 semiconductor substrate 1 and the nxe2x88x92 semiconductor layer 3, and the logic circuit 103 is formed in the surface of the nxe2x88x92 semiconductor layer 3 above the n+ buried impurity region 2. Near the end portion of the n+ buried impurity region 2, an n+ impurity region 5 extending from the surface of the nxe2x88x92 semiconductor layer 3 to the n+ buried impurity region 2 is formed to surround the logic circuit 103.
The n+ impurity region 5 includes n+ impurity regions 5a and 5b. The n+ impurity region 5a is formed in the surface of the nxe2x88x92 semiconductor layer 3 and connected to a metal electrode 55 which will be later described. The n+ impurity region 5b is connected to the n+ impurity region 5a and extends to the n+ buried impurity region 2.
On the side of the n+ impurity region 5 opposite the logic circuit 103, a p+ impurity region 7 is formed in the surface of the nxe2x88x92 semiconductor layer 3, apart from the n+ impurity region 5, to surround the logic circuit 103 and the n+ impurity region 5. In the surface of the nxe2x88x92 semiconductor layer 3 between the p+ impurity region 7 and the n+ impurity region 5, an oxide film 12 is formed, on which an electrode 19b is formed. This electrode 19b forms a so-called xe2x80x9cmultiple field platexe2x80x9d for improved breakdown voltage.
The logic circuit 103 comprises, for example, a p-channel MOSFET 130. The p-channel MOSFET 130 comprises a p+ drain region 31, a p+ source region 32, and a gate electrode 36. The drain region 31 and the source region 32 are formed with predetermined spacing in the surface of the nxe2x88x92 semiconductor layer 3, and the gate electrode 36 is formed through a gate insulating film 34 on the nxe2x88x92 semiconductor layer 3 between the drain and source regions 31 and 32. Further in the surface of the nxe2x88x92 semiconductor layer 3, an n+ impurity region 30 is formed adjacent to the drain region 31 with the oxide film 12 in between.
Apart from the buried impurity region 2, a buried impurity region 28 is selectively formed at the interface between the pxe2x88x92 semiconductor substrate 1 and the nxe2x88x92 semiconductor layer 3. Extending from this buried impurity region 28 to the surface of the nxe2x88x92 semiconductor layer 3, an n+ impurity region 45 is formed which is a cathode region of the bootstrap diode 102. The n+ impurity region 45 includes n+ impurity regions 45a and 45b. The n+ impurity region 45a is formed in the surface of the nxe2x88x92 semiconductor layer 3 and connected to the cathode electrode 15 which will be later described. The n+ impurity region 45b is connected to the n+ impurity region 45a and extends to the n+ buried impurity region 28.
A p+ impurity region 6, which is an anode region of the bootstrap diode 102, is formed apart from the p+ impurity region 7 in the surface of the nxe2x88x92 semiconductor layer 3 to surround the n+ impurity region 45. In the surface of the nxe2x88x92 semiconductor layer 3 between the n+ impurity region 45 and the p+ impurity region 6, the oxide film 12 is formed, on which an electrode 19a is formed. This electrode 19a also forms a multiple field plate.
Between the p+ impurity regions 6 and 7, a p+ impurity region 4 extending from the interface between the pxe2x88x92 semiconductor substrate 1 and the nxe2x88x92 semiconductor layer 3 to the surface of the nxe2x88x92 semiconductor layer 3 is formed in connection only with the p+ impurity region 7. The p+ impurity region 4 is formed to surround the n+ impurity region 45 and the p+ impurity region 6 and to surround the p+ impurity region 7, the n+ impurity region 5, and the logic circuit 103. That is, the bootstrap diode 102 and the high-potential island region 101 are isolated by the p+ impurity region 4.
The insulating film 18 is formed to cover the nxe2x88x92 semiconductor layer 3, the oxide film 12, the gate electrode 36, and the electrodes 19a and 19b. Through the insulating film 18, the anode electrode 16 is connected to the p+ impurity region 6, the cathode electrode 15 to the n+ impurity region 45, and the metal electrode 55 to the n+ impurity region 5. A metal electrode 35 is connected through the insulating film 18 to the drain region 31, the source region 32, the gate electrode 36, and the n+ impurity region 30. The cathode electrode 15 is connected by the metal electrode 14 to the metal electrode 55 and further to the metal electrode 35 on the drain region 31 and the n+ impurity region 30. This provides connection for the cathode of the bootstrap diode 102 and the logic circuit 103 as shown in FIG. 29. A floating metal electrode 50 is located on the insulating film 18 above the electrode 19a and its capacitive coupling to the electrode 19a improves the breakdown voltage. The insulating film 8 is formed on the insulating film 18 to cover the respective electrodes.
Now, an isolation region 104 and a region 105 of FIG. 30 will be set forth. The logic circuit 103 is surrounded by the n+ impurity region 5 and further by the p+ impurity region 4 outside the n+ impurity region 5. The nxe2x88x92 semiconductor layer 3 between the p+ impurity region 4 and the n+ impurity region 5 is covered with a depletion layer due to the RESURF effect. More specifically, for example when the pxe2x88x92 semiconductor substrate 1 and the p+ impurity region 4 are connected to a ground potential and a positive voltage is applied to the nxe2x88x92 semiconductor layer 3 and the nxe2x88x92 impurity region 5, a negative voltage is applied to a pn junction of the pxe2x88x92 semiconductor substrate 1, the p+ impurity region 4, the nxe2x88x92 semiconductor layer 3, and the n+ impurity region 5. A resultant RESURF effect leads to the formation of a depletion layer across the whole nxe2x88x92 semiconductor layer 3 between the p+ impurity region 4 and the n+ impurity region 5. The isolation region 104 refers to a region where the depletion layer is formed. Here, the logic circuit 103 is surrounded by the n+ impurity region 5 and the p+ impurity region 4 or, in other words, it is surrounded by the isolation region 104 as shown in FIG. 30.
Similarly, the RESURF effect leads to the formation of a depletion layer across the whole nxe2x88x92 semiconductor layer 3 between the n+ impurity region 45 and the p+ impurity region 4. That is, a depletion layer covers almost the whole of the nxe2x88x92 semiconductor layer 3 which is surrounded by the p+ impurity region 4 and where the bootstrap diode 102 is formed. The region 105 refers to a region where the depletion layer is formed.
The conventional HVIC 110 with the aforementioned configuration achieves a high breakdown voltage because even the surface of the nxe2x88x92 semiconductor layer 3 is covered with a depletion layer due to the RESURF effect of the pxe2x88x92 semiconductor substrate 1 and the nxe2x88x92 semiconductor layer 3. Above the p+ impurity region 4 connected to the pxe2x88x92 semiconductor substrate 1, however, the metal electrode 14 is located to which for example a high voltage of several hundred volts is applied. This inhibits the spread of a depletion layer in the nxe2x88x92 semiconductor layer 3, posing a problem of breakdown voltage reduction.
A first aspect of the present invention is directed to a semiconductor device comprising: a semiconductor substrate of p-type; a semiconductor layer of n-type formed on the semiconductor substrate; a first impurity region of the p-type formed in the semiconductor layer, extending from a surface of the semiconductor layer to an interface of the semiconductor layer and the semiconductor substrate, to define an island region; a buried impurity region of the n-type formed apart from the first impurity region at the interface within the island region, the buried impurity region being of a higher concentration than the semiconductor layer; a semiconductor element formed in the surface of the semiconductor layer above the buried impurity region; and a diode having a second impurity region of the p-type and a third impurity region of the n-type, the second impurity region being formed in the surface of the semiconductor layer above the interface between the first impurity region and the buried impurity region, the third impurity region being formed in the surface of the semiconductor layer apart from and between the second impurity region and the semiconductor element, wherein a potential applied to the semiconductor substrate and the first impurity region is lower than that applied to the second impurity region and the third impurity region.
According to a second aspect of the present invention, in the semiconductor device of the first aspect, a depth of the second impurity region in a direction to the semiconductor substrate and a distance between the second impurity region and the first impurity region are determined to provide a desired emitter-collector breakdown voltage of a parasitic bipolar transistor in which the semiconductor substrate and the first impurity region serve as an emitter, the semiconductor layer as a base, and the second impurity region as a collector.
According to a third aspect of the present invention, the semiconductor device of either of the first and second aspects further comprises: a fourth impurity region of the p-type connected to the second impurity region and formed in the surface of the semiconductor layer, extending toward the third impurity region, the fourth impurity region being of a lower concentration than the second impurity region.
According to a fourth aspect of the present invention, in the semiconductor device of the third aspect, a depletion layer is formed across the whole of the fourth impurity region.
According to a fifth aspect of the present invention, in the semiconductor device of either of the first through fourth aspects, the first impurity region has a bent portion, and the second impurity region and the third impurity region are opposed to each other along the bent portion.
According to a sixth aspect of the present invention, in the semiconductor device of either of the first through fourth aspects, the second impurity region and the third impurity region are opposed to each other along the first impurity region, and the third impurity region is longer in length than the second impurity region along the surface of the semiconductor layer.
A seventh aspect of the present invention is directed to a semiconductor device comprising: a semiconductor substrate of p-type; a semiconductor layer of n-type formed on the semiconductor substrate; a first impurity region of the p-type formed in the semiconductor layer, extending from a surface of the semiconductor layer to an interface of the semiconductor layer and the semiconductor substrate, to define a first island region and a second island region; a buried impurity region of the n-type formed apart from the first impurity region at the interface of the semiconductor layer and the semiconductor substrate within the first island region; a semiconductor element formed in the surface of the semiconductor layer above the buried impurity region; a diode having a second impurity region of the p-type and a third impurity region of the n-type which are formed in the surface of the semiconductor layer within the second island region, the second impurity region being located closer to the semiconductor element than the third impurity region; a metal electrode connected to the third impurity region and passing over the second impurity region and the first impurity region to be connected to the semiconductor element; and a fourth impurity region of the p-type connected to the second impurity region and formed in the surface of the semiconductor layer to be located below the metal electrode, the fourth impurity region being of a lower concentration than the second impurity region, wherein a potential applied to the semiconductor substrate and the first impurity region is lower than that applied to the second impurity region and the third impurity region.
An eighth aspect of the present invention is directed to a semiconductor device comprising: a semiconductor substrate of p-type; a semiconductor layer of n-type formed on the semiconductor substrate; a first impurity region of the p-type formed in the semiconductor layer, extending from a surface of the semiconductor layer to an interface of the semiconductor layer and the semiconductor substrate, to define a first island region and a second island region; a buried impurity region of the n-type formed apart from the first impurity region at the interface of the semiconductor layer and the semiconductor substrate within the first island region, the buried impurity region being of a higher concentration than the semiconductor layer; a semiconductor element formed in the surface of the semiconductor layer above the buried impurity region; a diode having a second impurity region of the p-type and a third impurity region of the n-type which are formed in the surface of the semiconductor layer within the second island region; a metal electrode connected to the third impurity region and passing over the first impurity region to be connected to the semiconductor element; and a fourth impurity region of the p-type connected to the first impurity region and formed in the surface of the semiconductor layer to be located below the metal electrode, the fourth impurity region being of a lower concentration than the first impurity region, wherein a potential applied to the semiconductor substrate and the first impurity region is lower than that applied to the second impurity region and the third impurity region.
According to a ninth aspect of the present invention, in the semiconductor device of either of the seventh and eighth aspects, a depletion layer is formed across the whole of the fourth impurity region.
In the semiconductor device of the first aspect, since the potential applied to the semiconductor substrate and the first impurity region is lower than that applied to the second impurity region and the third impurity region, application of a reverse voltage to the diode leads to the spread of a depletion layer from a junction between the semiconductor layer and both the semiconductor substrate and the first impurity region to the semiconductor layer. The semiconductor element is thus covered with the depletion layer, gaining protection.
The semiconductor device of the second aspect achieves a desired emitter-collector breakdown voltage of the parasitic bipolar transistor. This improves the breakdown voltage of the semiconductor device.
In the semiconductor device of the third aspect, the p-type fourth impurity region of a lower concentration than the second impurity region is connected to the second impurity region and extends toward the third impurity region. Thus, holes existing in the vicinity of the third impurity region are drawn back to the fourth impurity region. This shortens a recovery operating time for the diode.
In the semiconductor device of the fourth aspect, the whole of the fourth impurity region is covered with a depletion layer, which improves the breakdown voltage.
In the semiconductor device of the fifth aspect, the second impurity region and the third impurity region are opposed to each other along the bent portion of the first impurity region. Thus, even when the second impurity region is larger in area than the third impurity region, holes from the second impurity region are hard to enter the semiconductor element. This reduces unstable operations of the semiconductor device caused by hole injection.
In the semiconductor device of the sixth aspect, since the third impurity region is longer in length than the second impurity region along the surface of the semiconductor layer, holes from the second impurity region are hard to enter the semiconductor element. This reduces unstable operations of the semiconductor device caused by hole injection.
In the semiconductor device of the seventh aspect, since the fourth impurity region connected to the second impurity region is formed below the metal electrode, application of a reverse voltage to the diode leads to the formation of a depletion layer extending from a junction of the fourth impurity region and the semiconductor layer. Thus, even if application of a high voltage to the metal electrode which passes over the first impurity region inhibits the spread of the depletion layer in the semiconductor layer, breakdown voltage reduction can be minimized.
In the semiconductor device of the eighth aspect, since the fourth impurity region connected to the first impurity region is formed below the metal electrode and a lower potential is applied to the semiconductor substrate and the first impurity region than to the second impurity region and the third impurity region, application of a reverse voltage to the diode leads to the formation of a depletion layer extending from a junction of the fourth impurity region and the semiconductor layer. Thus, even if application of a high voltage to the metal electrode which passes over the first impurity region inhibits the spread of the depletion layer in the semiconductor layer, breakdown voltage reduction can be minimized.
In the semiconductor device of the ninth aspect, the formation of the depletion layer across the whole of the fourth impurity region further improves the breakdown voltage.
An object of the present invention is to provide a semiconductor device which minimizes breakdown voltage reduction caused by the metal electrode to which a high voltage is applied.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.